Frequency synthesis device and method

ABSTRACT

A frequency synthesis device including: a first generator configured to generate a periodic signal of frequency f 1 ; a second and third generator, coupled with the first generator and configured to receive as an input the periodic signal of frequency f 1  and to generate a signal S G  corresponding to a train of oscillations of frequency substantially equal to N·f 1 , of a time less than T 1 =1/f 1  and repeated periodically at the frequency f 1 , where N is a whole number greater than 1; and a fourth generator configured to generate, from the signal S G , a periodic signal wherein a frequency spectrum includes a primary line of frequency f 2 =(N+i)·f 1 , where i is a whole number.

FIELD OF THE INVENTION

The invention relates to a frequency synthesis device and method forsupplying a stable signal of a predetermined frequency from a signal oflower frequency. The invention also relates to a device for transmittingand/or receiving signals, operating for example in the radiofrequency(RF) range, comprising such a frequency synthesis device for outputtinga stable periodic signal.

STATE OF THE RELATED ART

A frequency synthesis device is suitable for supplying afrequency-stable signal intended to be used for example in an RFcommunication system. In this way, during a signal transmission, asignal containing the information to be sent can be modulated with thefrequency-stable signal acting as the carrier signal for conveying theinformation.

The frequency synthesis performed defines in this case the value of thetransmission carrier frequency. During signal reception, frequencysynthesis makes it possible to supply this frequency-stable signal todemodulate the information received.

A first example of an embodiment of a frequency synthesis device 10,used for example in a carrier frequency transmission/reception system,is shown in FIG. 1.

The device 10 comprises a voltage-controlled oscillator 12 (VCO),outputting a sinusoidal signal wherein the oscillation frequency iscontrolled by a voltage applied at the input of the oscillator 12. Theoscillator 12 is embodied such that it can output an oscillating signalin the band of frequencies used by the communication system includingthe device 10.

The oscillator 12 is considered to output a sinusoidal signal having thefrequency f₁.

The output signal supplied by the oscillator 12 alone is unstable in theRF and microwave frequency bands, drifts over time and has a highspectral impurity (phase noise). It thus needs to be stabilised inrespect of frequency by locking (i.e. by setting, or synchronising) thephase thereof on that of a very frequency-stable signal supplied forexample by a very high-quality resonator, such as a quartz resonator,operating however at a lower frequency (generally in the MHz range).

In order to lock the signal phase output by the oscillator 12 and thusstabilise the oscillation frequency f₁ of this signal, the oscillator 12is controlled within a phase-locked loop (PLL). This PLL comprises aplurality of serially interconnected frequency dividers (represented inthe form of a single element referenced 14 in FIG. 1) and suitable fordividing together the frequency f₁ of the signal output by theoscillator 12 by a whole or fractional number N.

At the output of the frequency dividers 14, a periodic signal offrequency f₁/N is obtained, which is then compared to a very stablereference periodic signal, such as a signal having a frequencyf_(quartz) supplied by a quartz resonator 16. The frequency dividers 14are embodied such that the factor N obtained enables the frequency f₁/Nto be close to the frequency f_(quartz). These two signals are comparedby a phase comparator 18 (or PFD for “Phase Frequency Detector”)generating an output signal proportional to the phase differencemeasured between these two signals and wherein the value is positive ornegative according to the sign of the difference f₁/N−f_(quartz). Thisoutput signal is sent as an input to a charge pump circuit and a filter20 outputting a signal applied to the control input of the oscillator 12suitable for adjusting the oscillation frequency thereof such thatf₁/N=f_(quartz) once the loop has stabilised.

With such a frequency synthesis device 10, the frequency stability ofthe signal of frequency f₁ output by the oscillator 12, the driftthereof over time and the spectral purity thereof are essentiallydependent on the characteristics of the reference signal of frequencyf_(quartz) supplied by the resonator 16 and the division rank N of thefrequency dividers 14. Furthermore, the frequencies synthesised by thedevice 10 are also dependent on the oscillation frequency range of theoscillator 12 such that:f _(oscmin) <N·f _(quartz) <f _(oscmax)

f_(oscmin) and f_(oscmax) being respectively the minimum and maximumoscillation frequencies of the oscillator 12.

The oscillator 12 is for example embodied in the form of differentialcrossed pairs (resonator coupled with a negative resistance). Thefrequency dividers 14 use various architectures according to whetherthey are positioned at the start of a chain (close to the frequency f₁,i.e. at the end of the oscillator 12) or at the end of a chain, to alower frequency (close to the frequency f_(quartz), i.e. at the end ofthe phase frequency detector 18). At high frequencies, the frequencydividers use CML (Current Mode Logic) or ILFD (Injection LockedFrequency Divider) type circuits. Frequency dividers operating at lowerfrequencies use merely numeric counter type architectures. The circuitsacting as the frequency dividers 14 may be programmable so that thevalue of the frequency synthesised by the device 10 is programmable (f₁is as such a multiple of f_(quartz)) via the choice of the value of N(the value of f_(quartz) is dependent on the type of resonator 16 and isthus not programmable).

This type of frequency synthesis device 10 involves the major drawbackof using a long chain of frequency dividers 14 given the high value of Nwhen the difference between f_(quartz) and f₁ is great. The firstfrequency dividers (those at the oscillator 12 end) operating at highfrequencies have a high static electricity consumption. Furthermore,when the first frequency dividers use an ILFD type architecture, in thiscase, they use resonant elements (inductors or transmission lines)occupying a large circuit area.

Moreover, the PLL uses feedback acting on the oscillation frequency ofthe oscillator 12. However, this feedback may give to instabilities inthe PLL (non-locking of the frequency f₁) in that this loop operates ata high frequency.

A second example of an embodiment of a frequency synthesis device 30,used in a high carrier frequency transmission/reception system (RFrange), is represented in FIG. 2.

In relation to the device 10 described above, this second frequencysynthesis device 30 uses an opposite approach consisting of multiplyingthe reference frequency f_(quartz) until the required frequency f₁ isobtained. As shown in FIG. 2, such a device 30 comprises a resonator 16,for example similar to that of the device 10 described above, outputtingthe reference stable signal of frequency f_(quartz). This signal isapplied at the input of a chain of frequency multiplier circuits 32 ofrank N (shown in the form of a single element in FIG. 2) suitable foroutputting the signal of frequency f₁=N.f_(quartz).

The device 30 does not comprise an oscillator or a phase-locked loop.The first frequency multiplier circuits 32 (those situated at theresonator 16 end) operate at low frequencies and use standard numericarchitectures. On the other hand, the frequency multiplier circuits 32situated at the end of the chain operate at high frequencies and usesubharmonic locking architectures, or make use of “push-push”,distortion, harmonic amplification or other techniques. The stabilityand purity of the signal (phase noise) of frequency f₁ obtained at theoutput of the frequency synthesis device 30 are essentially dependent onthe characteristics of the stable reference signal supplied by theresonator 16 and the multiplication rank N.

When the multiplication rank N is high (which is the case for afrequency synthesis device including in an RF communication system), itis necessary to use a large number of frequency multiplier circuits toproduce the chain 32, giving rise to a high consumption and largeoccupied circuit area. Furthermore, there is no programmable frequencymultiplier circuit, rendering the rank N fixed and not enabling thedevice 30 to synthesise frequencies in a programmable manner.

A third example of an embodiment of a frequency synthesis device 40,used for example in a high carrier frequency transmission/receptionsystem (RF), is shown in FIG. 3.

The architecture of the device 40 consists of a combination of thearchitectures of the frequency synthesis devices 10 and 30 describedabove. A first frequency synthesis is performed at the frequency f₁using a similar architecture to that of the device 10 (making use ofelements equivalent to the elements 12, 14, 16, 18, 20 of the device10). The frequency signal f₁ is then multiplied by a chain of frequencymultiplier circuits 42 of rank K in order to obtain an output signal offrequency f₂=K.f₁=K.N.f_(quartz).

Such a device 40 has the advantage of being capable of synthesisingprogrammable frequencies (via the programming of the parameter N) andincreasing the value of the frequency suitable for being obtained at theoutput. The frequencies suitable for being synthesised are such that:f _(oscmin) <N·K·f _(quartz) <f _(oscmax)

Although the frequency synthesis device 40 solves some of the drawbacksof the frequency synthesis devices 10 and 30, all these frequencysynthesis devices involve the drawback of making use of complete chainsof frequency dividers and/or multipliers of high ranks (N and K suitablefor being in the region of several hundred or several thousand), due tothe major differences between the carrier frequency values to beobtained at the output of the devices and the relatively low frequenciessuitable for being supplied by stable resonators such as quartzresonators.

However, these complete frequency divider or multiplier circuit chainshave a high electricity consumption and also occupy a large circuitarea.

DESCRIPTION OF THE INVENTION

One aim of the invention is that of providing a novel type of frequencysynthesis device not involving the drawbacks of the frequency synthesisdevices of the prior art described above.

For this, it relates to a frequency synthesis device, comprising atleast:

-   -   first means suitable for generating a periodic signal of        frequency f₁,    -   second means suitable for generating a periodic pulse signal        wherein a central frequency f_(G) is equal to N.f₁, where N is a        whole number greater than 1,    -   third means coupled with the first and second means, suitable        for receiving as an input the periodic signal of frequency f₁        and actuating the generation of the periodic pulse signal by the        second means merely on a portion of each period of the periodic        signal of frequency f₁,    -   fourth means suitable for generating, using the periodic pulse        signal output by the second means, a periodic, for example        sinusoidal, signal of frequency f₂=(N+i).f₁, where i is a whole        number.

The present invention further relates to a frequency synthesis device,comprising at least:

-   -   first means, or first generator, suitable for generating a        periodic signal of frequency f₁,    -   second and third means, or a second generator, coupled with the        first means and suitable for receiving as an input the periodic        signal of frequency f₁ and generating a signal S_(G)        corresponding to a train, or a set, of oscillations of frequency        substantially equal to N.f₁, of a time less than T₁=1/f₁ and        repeated periodically at the frequency f₁, where N is a whole        number greater than 1,    -   fourth means, or a third generator, suitable for generating,        from the signal S_(G), a periodic, for example sinusoidal,        signal, wherein the frequency spectrum comprises a primary line,        or primary peak, of frequency f₂=(N+i).f₁, where i is a whole        number.

Such a device is suitable for carrying out frequency synthesis which isstabilised in respect of frequency and noise. This device is based on afrequency multiplication of a signal, or more specifically a generation,using a low frequency, of a complex periodic signal centred at a higherfrequency, and a subsequent frequency recovery so as to obtain astabilised signal in respect of frequency. Indeed, the second and thirdmeans generate, for example via the control carried out by the thirdmeans on the second means, a periodic pulse signal wherein the centralfrequency f_(G) is a multiple of a first generated signal of frequencyf₁. The third means may actuate the second means as a control switchoperating at the frequency f₁. In this way, the spectrum of the signaloutput by the second means and third means, corresponding for example toa sinusoidal pulse signal, or more generally a signal corresponding toan oscillations train of frequency substantially equal to N.f₁, of atime T_(H) less than T₁=1/f₁ and repeated periodically at the frequencyf₁, where N is a whole number greater than 1, comprises a plurality oflines centred about the central frequency f_(G)=N.f₁ and at intervals off₁. The fourth means then serve to recover, in this spectrum, the soughtline and generate a stable periodic signal, for example sinusoidal orhaving a substantially sinusoidal shape, of central frequencyf₂=(N+i).f₁.

The device according to the invention is thus suitable for carrying outhigh-frequency synthesis (f₂) using a low-frequency signal (frequencyf₁) and a high-frequency pulse generator formed by the second and thirdmeans.

The device according to the invention is suitable for carrying out,between the frequency f₁ and the frequency f₂ output, a high-rankingfrequency multiplication without involving the drawbacks of thefrequency multipliers of the prior art. The device according to theinvention does not use a conventional frequency multiplier chain as insome of the frequency synthesis devices according to the prior art andthus has the advantage of reducing the consumption and size of thefrequency synthesis device. Furthermore, the frequency synthesised isprogrammable by programming the parameters N and i.

The device according to the invention thus has the advantage, inrelation to the frequency synthesis devices according to the prior artcomprising long frequency multiplier or divider chains, of reducing theelectricity consumption of the device, enhancing the performances of thefrequency synthesis carried out in terms of phase noise and frequencyoperating range, and also reducing the complexity of the design of thedevice.

The frequency synthesis device according to the invention does notrequire a long frequency divider chain (giving rise to high consumptionand a large occupied area), or a PLL operating at high frequency (givingrise to instabilities at high frequencies).

The signal output by the fourth means may correspond to a periodicsignal wherein the frequency spectrum comprises lines of whole multiplefrequencies of f₁ and wherein the primary line (exhibiting the greatestamplitude from the set of spectral lines) is at the frequencyf₂=(N+i)f₁.

The invention also relates to a frequency synthesis device comprising atleast:

-   -   means suitable for generating a periodic signal of frequency f₁,    -   means suitable for generating, from the periodic signal of        frequency f₁, a periodic pulse signal wherein a central        frequency f_(G) is equal to N.f₁, where N is a whole number        greater than 1, the periodic pulse signal periodically having a        zero value on a portion of the period of the periodic signal of        frequency f₁,    -   means suitable for generating, from the periodic pulse signal of        central frequency f_(G) equal to N.f₁, a periodic, for example        sinusoidal, signal of frequency f₂=(N+i).f₁, where i is a whole        number.

The second means may comprise at least one voltage-controlled oscillatorwherein the free oscillation range includes the central frequency f_(G),i.e. N.f₁, the value of N optionally being dependent on a value of afirst control voltage to be applied at the input of thevoltage-controlled oscillator. The free oscillation range may be definedas being the frequency range between the minimum frequency and themaximum frequency suitable for being reached by the voltage-controlledoscillator according to the first control voltage.

The third means may be suitable for generating a supply voltage of thesecond means in the form of a further periodic signal of frequency f₁wherein the cyclic ratio may be less than 1.

The third means may comprise at least one switch connected to anelectrical power supply input of the second means and suitable for beingcontrolled by the periodic signal of frequency f₁ to be generated by thefirst means.

The third means may comprise at least one switch connected to anelectrical power supply input of the oscillator and suitable for beingcontrolled by the periodic signal of frequency f₁ such that it generatesa non-zero oscillator power supply voltage merely during a portion ofeach period T₁.

The third means may comprise at least one switch connected to anoscillator output and suitable for being controlled by the periodicsignal of frequency f₁ such that it breaks an electrical connectionbetween the oscillator output and the input of the fourth means during aportion of each period T₁.

The fourth means may comprise at least one injection-locked oscillatorintended to receive, as an input, the periodic pulse signal of centralfrequency f_(G) (which is periodically interrupted at the frequency f₁)generated by the second means, or the signal S_(G), and to be locked atleast periodically at the frequency f₂, the value of i optionally beingdependent on a value of a second control voltage intended to be appliedat the input of the injection-locked oscillator. This/theseinjection-locked oscillators may carry out recovery of at least one ofthe lines, corresponding to the frequency f₂, of the spectrum of thesignal output by the second means.

The fourth means may comprise at least one band-pass filter of centralfrequency substantially equal to f₂.

The value of the frequency f₁ may be greater than approximately 1 GHz,and/or the value of the frequency f₂ may be greater than approximately10 GHz, and/or the periodic pulse signal generated by the second meansmay be a sinusoidal pulse signal, and/or the oscillations of the signalS_(G) may be sinusoidal, and/or the periodic signal of frequency f₂, ormore generally the periodic signal wherein the frequency spectrumcomprises a primary line of frequency f₂, may be a substantiallysinusoidal signal.

The first means may comprise at least one resonating device and aphase-locked loop suitable for controlling the phase of the periodicsignal of frequency f₁ output by a voltage-controlled oscillator of thephase-locked loop on a phase of a periodic signal, for example asinusoidal signal, output by the resonating device. In this way, thefrequency synthesis device may make use of a phase-locked loop operatingat a low frequency, making it possible to eliminate the risks ofinstability induced by a PLL operating at a high frequency as in theprior art.

Alternatively, the first means may also comprise a resonating devicesuitable for generating the periodic signal, which is stable, offrequency f₁.

The invention also relates to a signal transmission and/or receptiondevice, comprising at least one frequency synthesis device as definedabove and coupled with a modulator and/or a demodulator of thetransmission and/or reception device.

The invention also relates to a frequency synthesis method, comprisingat least steps for:

-   -   generating a periodic signal of frequency f₁,    -   generating, from the periodic signal of frequency f₁, a periodic        pulse signal wherein a central frequency f_(G) is equal to N.f₁,        where N is a whole number greater than 1, the periodic pulse        signal having periodically a non-zero value merely on a portion        of each period of the periodic signal of frequency f₁,    -   generating, from the periodic pulse signal of central frequency        f_(G), a periodic signal of frequency f₂=(N+i).f₁, where i is a        whole number.

The present invention further relates to a frequency synthesis method,comprising at least steps for:

-   -   generating a periodic signal of frequency f₁,    -   generating, from the periodic signal of frequency f₁, a signal        S_(G) corresponding to a train, or a set, of oscillations of        frequency substantially equal to N.f₁, of a time less than        T₁=1/f₁ and repeated periodically at the frequency f₁, where N        is a whole number greater than 1,    -   generating, from the signal S_(G), a periodic signal of        frequency f₂=(N+i).f₁, where i is a whole number.

The fact that the periodic pulse signal generated by the second meanshas a non-zero value merely on a portion of each period of the periodicsignal of frequency f₁ means that this pulse signal periodically has azero value on a portion of the period of the periodic signal offrequency f₁.

The present invention also relates to a frequency synthesis method,comprising at least steps for:

-   -   generating a periodic signal of frequency f₁,    -   generating, from the periodic signal of frequency f₁, a signal        S_(G) corresponding to a train, or a set, of oscillations of        frequency substantially equal to N.f₁, of a time less than        T₁=1/f₁ and repeated periodically at the frequency f₁, where N        is a whole number greater than 1,    -   generating, from the signal S_(G), a periodic signal wherein the        frequency spectrum comprises a primary line of frequency        f₂=(N+i).f₁, where i is a whole number.

The invention also relates to a method for producing a frequencysynthesis device, comprising at least steps for:

-   -   producing first means suitable for generating a periodic signal        of frequency f₁,    -   producing second means suitable for generating a periodic pulse        signal wherein a central frequency f_(G) is equal to N.f₁, where        N is a whole number greater than 1,    -   producing third means coupled with the first and second means,        suitable for receiving, as an input, the periodic signal of        frequency f₁ and controlling the generation of the periodic        pulse signal by the second means merely on a portion of each        period of the periodic signal of frequency f₁,    -   producing fourth means suitable for generating, from the        periodic pulse signal output by the second means, a periodic        signal of frequency f₂=(N+i).f₁, where i is a whole number.

The invention finally relates to a method for producing a frequencysynthesis device, comprising at least steps for:

-   -   producing first means suitable for generating a periodic signal        of frequency f₁,    -   producing second and third means, coupled with the first means        and suitable for receiving as an input the periodic signal of        frequency f₁ and generating a signal S_(G) corresponding to a        train, or a set, of oscillations of frequency substantially        equal to N.f₁, of a time less than T₁=1/f₁ and repeated        periodically at the frequency f₁, where N is a whole number        greater than 1,    -   producing fourth means suitable for generating, from the signal        S_(G), a periodic signal wherein the frequency spectrum        comprises a primary line of frequency f₂=(N+i).f₁, where i is a        whole number.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will be understood more clearly on reading thedescription of examples of embodiments given merely as an indication andbeing in no way limiting with reference to the appended figures wherein:

FIGS. 1 to 3 schematically represent frequency synthesis devicesaccording to the prior art,

FIG. 4 schematically represents a frequency synthesis device, accordingto the present invention, according to a first embodiment,

FIGS. 5A and 5B respectively represent the waveform and the spectrum ofa signal S_(C) generated in a frequency synthesis device, according tothe present invention,

FIGS. 6A and 6B respectively represent the waveform and the spectrum ofa signal S_(G) generated in a frequency synthesis device, according tothe present invention,

FIGS. 7A and 7B respectively represent the waveform and the spectrum ofa signal S₂ obtained at the output of a frequency synthesis device,according to the present invention,

FIG. 8 represents the selectivity of a frequency recovery circuitincluded in a frequency synthesis device, according to the presentinvention,

FIGS. 9A and 9B represent waveforms and spectra of the signals generatedin a frequency synthesis device, according to the present invention,

FIG. 10 represents the spectrum of a signal S_(G) generated in afrequency synthesis device, according to the present invention,according to one example of an embodiment,

FIG. 11 represents the spectrum of a signal S₂ obtained at the output ofa frequency synthesis device, according to the present invention,according to one example of an embodiment,

FIG. 12 represents the phase noise of a signal S₂ obtained at the outputof a frequency synthesis device, according to the present invention,according to one example of an embodiment,

FIG. 13 schematically represents a communication system, also accordingto the present invention, comprising a frequency synthesis deviceaccording to the invention;

FIGS. 14A and 14B represent signals S₂ obtained at the output of afrequency synthesis device, according to the present invention,according to one example of an embodiment;

FIG. 15 schematically represents a frequency synthesis device, accordingto the present invention, according to a second embodiment.

Identical, similar or equivalent parts of the various figures describedhereinafter bear the same reference numbers for easier transition fromone figure to another.

The various parts represented in the figures are not necessarily basedon a uniform scale, so as to render the figures more legible.

The various options (alternatives and embodiments) should be understoodas not being mutually exclusive and suitable for being combined witheach other.

DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

Reference is first made to FIG. 4 representing a frequency synthesisdevice 100 according to a first embodiment.

The device 100 comprises an oscillator 102 for example of the VCO typeoutputting a periodic signal S₁ of frequency f₁, for example sinusoidalof oscillation frequency f₁. The frequency f₁ is controlled by a voltageapplied on a control input 104 of the oscillator 102. In order to lockand stabilise the oscillation frequency f₁ of the signal S₁, theoscillator 102 is controlled by a phase-locked loop (PLL). This PLLcomprises one or a plurality of frequency dividers 106 suitable fordividing the frequency of the signal S₁ by a whole or fractional numberA. At the output of the frequency divider(s) 106, a periodic signal offrequency f₁/A which is then compared to a very stable referenceperiodic signal of frequency f_(stable) supplied by a resonator 108, forexample a quartz resonator is obtained. The factor A is chosen such thatthe frequency f₁/A is close to the frequency f_(stable). These twosignals are compared by a phase frequency detector 110 (PFD) generatingan output signal proportional to the phase difference measured betweenthese two signals, wherein the value is positive or negative accordingto the sign of the difference f₁/A−f_(stable).

This output signal is sent as an input to a charge pump circuit and afilter 112 outputting the signal applied to the control input 104 of theoscillator 102 so as to adjust the oscillation frequency f₁, such thatf₁/A=f_(stable).

The elements 102, 106, 108, 110 and 112 are suitable for obtaining aperiodic, for example sinusoidal, signal S₁, which is stable in respectof frequency. Alternatively, it is possible to replace these elements102, 106, 108, 110 and 112 by any device or structure suitable forsupplying such a frequency-stable periodic signal S₁, corresponding forexample to a single resonating device if such a resonating device cansupply the signal S₁ directly. The choice of the type of device orstructure generating the periodic signal S₁ may notably be performedaccording to the sought frequency f₁. A resonating device alone may besufficient if the frequency f₁ does not exceed a value above which itmay then be necessary to make use of a PLL to generate the signal S₁.

The frequency synthesis device 100 further comprises a generator of aperiodically repeated oscillations train (hereinafter referred to as“PROT”) in the band of frequencies to be synthesised and a frequencyrecovery device.

In this first embodiment, the PROT generator comprises a VCO typeoscillator 114 voltage-controlled by a control signal V_(ctrl), andcontrolled electrical power supply means 116 electrically powering theoscillator 114 and which are controlled by the signal S₁ of frequency f₁output by the oscillator 102.

In the example in FIG. 4, this controlled electrical power supplycorresponds to a controlled current source 116 operating as a switchperiodically breaking (period T₁=1/f₁) the electrical power supply ofthe oscillator 114. This controlled current source may corresponds to anMOS transistor comprising a gate whereon the signal S₁ is applied. As ageneral rule, these means 116 may comprise a switch connected to anelectrical power supply input of the oscillator 114 and suitable forbeing controlled by the periodic signal S₁.

The oscillator 114 is thus switched by this switch alternatively settingthe oscillator 114 to ON and OFF, i.e. breaking or not the supply of anoutput signal by the oscillator 114, successively at the frequency f₁.The oscillator 114 is controlled by a signal S_(C) corresponding to thecurrent generated by the current source 116 (and thus to the powersupply voltage supplied to the oscillator 114) and wherein the waveformsubstantially corresponds to a positive square signal of frequency f₁(this square signal is not perfect and may have a trapezoidal shape, asis the case of the signal S_(C) represented in FIG. 5A). In this way,when the switching signal S_(C) starts up the oscillator 114, a signalS_(G) corresponding to an oscillations train is created at the VCOoutput. A half-period T₁/2 (where T₁=1/f₁) later, the oscillator 114 isswitched off and the oscillation is interrupted. Alternating the ON andOFF every half-period T₁/2 corresponds to the scenario where the signalS_(C) has a cyclic ratio equal to 0.5. The signal S_(C) represented inFIG. 5A switches on the oscillator 114 for a time T_(H) which is equal,in this example, to T₁/2.

However, this cyclic ratio (equal to T_(H)/T₁) may be different to 0.5,and more generally between 0 and 1, the values 0 and 1 being excluded,the time of the ON state optionally being greater or less than that ofthe OFF state.

In this way, a pulsed signal S_(G) is created at a central frequencyf_(OL), corresponding to the free oscillation frequency of theoscillator 114, with a repetition period equal to T₁. The signal S_(G)thus corresponds to a PROT, i.e. in this instance a train, or a set, ofoscillations of frequency f_(OL), of a time less than T₁=1/f₁ andrepeated periodically with a repetition period equal to T₁. The signalS_(G) thus periodically has a zero value on a portion of each period T₁,this portion of each period T₁ corresponding approximately to theportion of each period T₁ during which the signal S_(C) has a zerovalue. The signal S_(G) has the specificity of having the phase thereoflocked on that of the signal of frequency f₁ supplied by the oscillator102 and has a central frequency f_(OL) which is substantially equal to awhole multiple of f₁ (f_(OL)≈N.f₁). This property is due to the factthat, on starting up oscillation, the oscillator 114 has a highelasticity and is locked readily on an harmonic N of the frequency f₁where N is such that the product N·f₁ is closest to the free oscillationfrequency f_(OL) of the oscillator 114 when in free oscillation. Thevalue of N, and thus that of the frequency f_(OL), are dependent on thevalue of the voltage V_(ctrl) applied at the input of the oscillator114.

The equivalent spectrum of the signal S_(G) has an envelope wherein theshape corresponds to a cardinal sine wherein the components aresinusoids of central frequency N.f₁. The lines of the spectrum of S_(G)are spaced at intervals of f₁. FIGS. 5A and 5B respectively representthe waveform (time domain) and the spectrum (frequency domain) of thesignal Sc.

Similarly, FIGS. 6A and 6B respectively represent the waveform and thespectrum of the signal S_(G). In FIG. 6A, it can be seen that in eachoscillations train of the signal S_(G), the amplitudes of theoscillations are increasing on starting the oscillator 114 and aredecreasing on switching off the oscillator 114.

Furthermore, the oscillations of the oscillations trains of S_(G) aresimilar, in terms of phase, amplitude and frequency, from one train toanother.

In analytical terms, the signal S_(G) is obtained by means ofconvolution in the time domain between a windowed sine, of frequencyf_(OL) (corresponding to the free oscillation frequency of theoscillator 114) and of window width equal to T_(H), where T_(H)ε]0, T₁[,and a Dirac comb of period equal to T₁. The signal S_(G) may thus beexpressed in the following form:

${S_{G}(t)} = {\left\lbrack {{\sin\left( {2 \cdot \pi \cdot f_{OL} \cdot t} \right)} \cdot {\prod\limits_{T_{H}}\;(t)}} \right\rbrack \otimes {\sum\limits_{k = {- \infty}}^{\infty}{\delta\left( {t - {k \cdot T_{1}}} \right)}}}$

Π_(T) _(H) (t) is the windowing function corresponding to:

${\prod\limits_{T_{H}}\;(t)} = \left\{ \begin{matrix}0 & {\forall{t < 0}} \\1 & {{\left. {\forall{t \in}} \right\rbrack 0},{T_{1}\lbrack}} \\0 & {\forall{t > T_{H}}}\end{matrix} \right.$

The frequency spectrum of the signal S_(G) corresponds in this case to:

${{S_{G}(f)}}_{f > 0} = {\left\lbrack {\frac{1}{2}{{{\delta\left( {f - f_{OL}} \right)} \otimes T_{H}} \cdot \sin}\;{c\left( {\pi \cdot f \cdot T_{H}} \right)}} \right\rbrack \cdot f_{1} \cdot {\sum\limits_{k = {- \infty}}^{\infty}{\delta\left( {f - {k \cdot f_{1}}} \right)}}}$

For each of the lines of frequency f_(i) of the spectrum of the signalS_(G) (f_(i) being multiples of f₁), the amplitude A_(i) of each ofthese lines may be expressed by the equation:

$A_{i\;} = {\frac{1}{2}\sin\;{c\left( {{\pi\left( {f_{i} - f_{OL}} \right)} \cdot T_{H}} \right)}}$

The signal S_(G) is then used to obtain at the output of the device 100a periodic, for example sinusoidal, signal S₂, wherein the frequencyspectrum comprises a primary lines, or peak, i.e. having a higher valuein relation to the other lines, of frequency f₂ corresponding to thefrequency to be synthesised by the device 100. In addition, in order toobtain a spectrum corresponding to, or approximating, a pure sinewithout the adjacent lines (corresponding to the lines at (N+x).f₁,where x is a whole number, on the spectrum of the signal S_(G)represented in FIG. 6B, when f₂=f_(OL)), the device 100 comprises afrequency recovery circuit 118, or line recovery circuit, wherein theinput is connected to the output of the pulsed oscillator 114. Thefrequency recovery circuit 118 acts as a band-pass filter and rejectsthe lines adjacent to the frequency to be recovered. At the output ofthe frequency recovery circuit 118, a periodic signal S₂ is obtainedwherein the primary line has the frequency f₂=f_(OL), for example asinusoidal signal with a substantially constant envelope wherein thefrequency f₂ is for example equal to N·f₁. The phase noise of the signalS₂ is equal to the phase noise of the signal S₁ plus 20 log(N), where Nis the multiplication factor between f₁ and f₂:PhN _(dBc/Hz) ^(f) ² =PhN _(dBc/Hz) ^(f) ¹ +20log(N)

FIGS. 7A and 7B respectively represent the waveform (time domain) andthe spectrum (frequency domain) of the signal S₂. As such, at the outputof the device 100, a signal S₂ having a pure spectrum is obtained, i.e.comprising a single line at the frequency f₂ locked on f_(stable), anyother undesired components having been rejected by the frequencyrecovery circuit 118.

The oscillators 102 and 114 are for example embodied in the form ofdifferential crossed pairs (resonators coupled with a negativeresistance). The oscillator 114 may for example be embodied as describedin the document “A 60 GHz UWB impulse radio transmitter with integratedantenna in CMOS65 nm SOI technology” by A. Siligaris et al., SiliconMonolithic Integrated Circuits in RF Systems (SiRF), 2011 IEEE 11thTopical Meeting on, pp. 153-156, 17-19 Jan. 2011. The oscillator 102 mayfor example be embodied as described in the document “A 17.5-to-20.94GHz and 35-to-41.88 GHz PLL in 65 nm CMOS for wireless HD applications”by O. Richard et al., Solid-State Circuits Conference Digest ofTechnical Papers (ISSCC), 2010 IEEE International, pp. 252-253, 7-11Feb. 2010.

The frequency recovery circuit 118 acts as a very high-selectivityband-pass filter, and may correspond to an injection locked, orsynchronised, oscillator circuit (ILO) or a plurality of ILO circuitsarranged in cascade. The embodiment of such an ILO is for exampledescribed in the document “A 50 GHz direct injection locked oscillatortopology as low power frequency divider in 0.13 μm CMOS” by M. Tiebout,Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the29th European, pp. 73-76, 16-18 Sep. 2003.

Such an oscillator circuit operates continuously and in the absence of asignal S_(G) applied at the input (when the signal S_(G) periodicallyhas a zero value), the circuit 118 outputs a sinusoidal free oscillationsignal wherein the frequency f_(osc) _(—) _(libre) _(—) ₁₁₈ is in thesame frequency band as f₂ (f_(osc) _(—) _(libre) _(—) ₁₁₈≈f₂). The valueof the frequency f_(osc) _(—) _(libre) _(—) ₁₁₈ is only dependent on thevalue of a control signal V_(ctrl) _(—) ₁₁₈ applied to another input ofthe frequency recovery circuit 118. When the first input is excited bythe pulsed signal S_(G) output by the oscillator 114, the frequencyrecovery circuit 118 is locked on the line of the signal S_(G) closestto f_(osc) _(—) _(libre) _(—) ₁₁₈. The control signal V_(ctrl) _(—) ₁₁₈is suitable for positioning f_(osc) _(—) _(libre) _(—) ₁₁₈ close to N·f₁so as to centre the signal S₂ exactly on N·f₁, i.e. f_(G), or on anadjacent line of N·f₁. It is thus possible to lock the frequencyrecovery circuit 118 on a line (N+1)·f₁, where i is a whole number(positive or negative of zero), if the control signal V_(ctrl) _(—) ₁₁₈is such that f_(osc) _(—) _(libre) _(—) ₁₁₈ is situated close to theline (N+i)·f₁.

The frequency f2 suitable for being synthesised by the device 100 isthus configurable and equal to:f ₂=(N+i)·f ₁

The programming, or setting, of the value of the frequency f₂synthesised is thus performed by means of the parameters N and/or iand/or f₁.

The parameters N and i may be modified by means of the value of thecontrol signal V_(ctrl) of the oscillator 114, and the value of thecontrol signal V_(ctrl) _(—) ₁₁₈ of the frequency recovery circuit 118.

A first option for programming the value of the frequency f₂ consists oflocking the oscillator 114 directly on the desired output frequency suchthat f_(OL)=f₂=N.f₁. Indeed, as explained above, the oscillator 114 hasa high elasticity and tends to be locked readily on a harmonic N of thefrequency f₁ at the beginning of the oscillations. The value of theoscillation frequency of the oscillator 114 f_(OL) is thus fixed bysetting the value of V_(ctrl) such that f_(OL)=f₂=N.f₁. The centralfrequency f_(OL) of the spectrum of the oscillator 114 is then locked onthe line N.f₁. The frequency recovery circuit 118 then sees at the inputthereof a signal S_(G) wherein the spectrum is a cardinal sine havinglines at intervals of f₁ wherein the central line is situated atf_(OL)=N.f1. The control signal V_(ctrl) _(—) ₁₁₈ of the frequencyrecovery circuit 118 is chosen so that the locking takes place on thecentral line, at the frequency f_(OL), i.e. where i=0. In this way, inthis first possible programming of the value of f₂, the value of thesynthesised frequency f2 is chosen by selecting the value of the controlsignal V_(ctrl) of the oscillator 114 (determining the value of N), thevalue of the control signal V_(ctrl) _(—) ₁₁₈ of the frequency recoverycircuit 118 being constant and chosen such that i=0).

A second option for setting the value of f₂ consists of locking theoscillator 114 on a frequency f_(OL)=N.f₁ where N is fixed (i.e.V_(ctrl) having a constant value). The spectrum of the output signalS_(G) is a cardinal sine having lines at intervals of f₁ wherein thecentral line is at the frequency f_(OL). The control signal V_(ctrl)_(—) ₁₁₈ of the frequency receiver circuit is then chosen so that thelocking takes place on one of the lines adjacent to the central linef_(OL) corresponding to the frequency f₂ sought (i.e. such that i≠0), inthe primary lobe of the cardinal sine spectrum. In this secondprogramming example, the value of the synthesised frequency f₂ is chosenby selecting the value of the control signal V_(ctrl) _(—) ₁₁₈ of thefrequency recovery circuit 118 (determining the value of i which isdifferent to 0), the value of the control signal V_(ctrl) of theoscillator 114 being constant and chosen such that the value of N issuch that the line of frequency f₂ is situated in the primary lobe ofthe cardinal sine spectrum having a central line at the frequency f_(OL)such that f_(OL)=N.f₁.

In a third option for programming the value of f₂, it is possible tocombine the two previous options. This involves adjusting both thecontrol signal V_(ctrl) of the oscillator 114 (adjusting the value of N)and the control signal V_(ctrl) _(—) ₁₁₈ of the frequency recoverycircuit 118 (adjusting the value of i) to synthesise the soughtfrequency f₂.

Regardless of the programming option chosen from those described above,the value of f₂ may also be modified by setting or selecting the valueof the frequency f₁ given that the value of f₁ corresponds to theinterval of the lines in the spectrum of the signal S_(G).

The frequency recovery circuit 118 is suitable for selecting a linesituated in the primary lobe of the spectrum of the signal S_(G) outputby the oscillator 114. It acts both as a very selective band-pass filterand as a signal regenerator, by means of the locking performed on thefrequency (N+i)f₁. The selectivity of the frequency recovery circuit118, when this corresponds to an injection locked oscillator (ILO) typecircuit, is represented in FIG. 8. The zone referenced 120 representsthe locking range of such an ILO which, in the example in FIG. 8, islocked on the central line of the spectrum of the signal S_(G) closestto the free oscillation frequency thereof.

The output signal of this ILO primarily comprises this line but therejection of adjacent lines is not infinite. As such, the signal S₂obtained at the output of the frequency recovery circuit 118 may notcorrespond to a pure sinusoidal signal, but to a periodic signal whereinthe envelope is never zero (unlike the signal S_(G) wherein the envelopeis periodically zero) and wherein the frequency spectrum exhibits aprimary line at the frequency f₂. The secondary lines of this spectrum,at multiple frequencies of f₁, are attenuated in relation to thesecondary lines of the spectrum of the signal S_(G).

FIG. 14A represents a spectrum of a signal S₂ obtained for example witha frequency recovery circuit 118 comprising a single ILO. It is possibleto increase this rejection by connecting, in cascade (i.e. in series),one or a plurality of further ILOs to form the frequency recoverycircuit 118 and thus attenuate the secondary lines of the spectrum ofthe signal S₂ further, suitable for enhancing the constancy of theenvelope of the signal S₂. FIG. 14B represents a spectrum of a signal S₂obtained for example with a frequency recovery circuit 118 comprising aplurality of ILOs connected in cascade. It can be seen in this figurethat the signal S₂ thus corresponds practically to a pure sinusoidalsignal.

In respect of the shape of the spectrum of the signal S_(G), the lowerthe cyclic ratio of this signal, the wider the primary lobe of thecardinal sine.

As such, a low cyclic ratio involves the presence of a greater number oflines in the primary lobe of the spectrum of the signal S_(G), and thusof more frequencies suitable for being synthesised by varying i for agiven N. This principle is illustrated in FIGS. 9A and 9B representingthe waveforms of the signals S_(C) and S_(G), and the spectrum of thesignal S_(G), for two signals S_(C) of different cyclic ratios α₁(=T_(H1)/T₁) and α₂ (=T_(H2)/T₁), the cyclic ratio α₁ of the signalS_(C) represented in FIG. 9A being greater than the cyclic ratio α₂ ofthe signal S_(C) represented in FIG. 9B.

Alternatively, the frequency recovery circuit 118 may correspond to oneor a plurality of band-pass filters connected in cascade. This/thesefilter(s) is/are embodied such that the central frequency thereof isclose to the line of signal S_(G) of frequency (N+i).f₁, suitable forfiltering the signal S_(G) and recovering the line of frequency (N+i).f₁corresponding to the frequency f₂ sought. This/these filter(s) is/arealso embodied such that they are very selective. This/these filter(s)may be embodied in a number of ways, for example in the form of BAW(bulk acoustic wave), LC (using inductors and capacitors) or SAW(surface acoustic wave) filters. Furthermore, it is also possible forthe frequency recovery circuit 118 to comprise one or a plurality ofILOs and one or a plurality of band-pass filters connected in cascade.

Reference is made to FIG. 15 representing a frequency synthesis device200 according to a second embodiment.

In relation to the device 100 described above, the oscillator 114 is nolonger controlled by a periodically interrupted power supply source, butis powered continuously, supplying a sinusoidal signal of frequencyf_(OL). This signal is sent to the input of a switch 202 controlled bythe periodic signal S₁. The switch 202 is periodically (period T₁) inthe closed position for a time equal to T_(H) (for example equal to T₁/2in the case of cyclic ratio of 0.5) and in the open position for a timeequal to T₁−T_(H).

In this case, at the input of the circuit 118, a PROT type signal S_(G)is obtained, i.e. a train of oscillations of frequency f_(OL)periodically repeated with a repetition period equal to T₁. Theoscillations of the oscillations trains of S_(G) are not generallysimilar, in terms of phase, from one train to another.

In analytical terms, this signal S_(G) corresponds to the product of asine of frequency f_(OL) (the free oscillation frequency of theoscillator 114) and a periodic square signal of period T₁ and ahigh-state time T_(H) where T_(H)ε]0, T₁[ such that:

${S_{G}(t)} = {{\sin\left( {2 \cdot \pi \cdot f_{OL} \cdot t} \right)} \cdot \left\lbrack {\prod\limits_{T_{H}}\;{(t) \otimes {\sum\limits_{k = {- \infty}}^{\infty}{\delta\left( {t - {k \cdot T_{1}}} \right)}}}} \right\rbrack}$

The frequency spectrum of the signal S_(G) corresponds in this case to:

${{S_{G}(f)}}_{f > 0} = {\frac{1}{2}{{\delta\left( {f - f_{OL}} \right)} \otimes \left\lbrack {{T_{H} \cdot \sin}\;{{c\left( {\pi \cdot f \cdot T_{H}} \right)} \cdot f_{1} \cdot {\sum\limits_{k = {- \infty}}^{\infty}{\delta\left( {f - {k \cdot f_{1}}} \right)}}}} \right\rbrack}}$

For each of the lines of frequencies f_(i) of the spectrum of the signalS_(G) (where f_(i)=f_(OL)+i.f₁), the amplitude A_(i) of each of theselines may be expressed by the equation:

$A_{i\;} = {\frac{T_{H}}{2 \cdot T_{1}}\sin\;{c\left( {{\pi \cdot i}\;\frac{T_{H}}{T_{1}}} \right)}}$

The various alternative embodiments of the frequency recovery circuit118 described above for the frequency synthesis device 100 may also beapplied to the frequency synthesis device 200.

An example of an embodiment of the frequency synthesis device 100 isdescribed hereinafter.

The PLL supplying the signal S₁, the current source 116 and theoscillator 114 along with the frequency recovery circuit 118 areembodied for example in 65 nm CMOS technology for example on SOI so asto obtain for example a frequency synthesis device according to theIEEE.802.15.3c standard relating to WPAN, WirelessHD or WiGig networks,wherein signal transmissions are for example carried out in a frequencyrange between approximately 57 GHz and 66 GHz.

The elements 102, 106, 108, 110 and 112 are embodied so as to obtain atthe output of the oscillator 102 a signal S₁ of frequency f₁ equal toapproximately 2.16 GHz with a reference signal f_(stable)=36 MHz. Theoscillator 114 is for example embodied so as to output a signal S_(G)wherein the spectrum is shown in FIG. 10. It can be seen in thisspectrum that the various lines, representing different possiblecommunication channels according to the communication standards, areindeed at intervals of f₁. The control voltages V_(ctrl) and V_(ctrl)_(—) ₁₁₈ are chosen such that the frequency recovery circuit 118 outputsa signal S₂ of frequency f₂=62.64 GHz (channel 3 of standards). Thespectrum of the signal S₂ obtained at the output of such a frequencysynthesis device 100 is represented in FIG. 11. Finally, the phase noiseof this signal S₂ is represented in FIG. 12. This also applies for theembodiment of the frequency synthesis device 200.

The frequency synthesis device 100 or 200 is for example used in an RFtransmission system 1000 of which an example of architecture isrepresented schematically in FIG. 13. The transmission system 1000comprises elements for transmitting signals such as a basebandprocessing circuit 1002 receiving as an input the information to betransmitted, a modulator 1004, a power amplifier 1006 and a transmittingantenna 1008. The frequency synthesis device 100 or 200 is used inconjunction with the modulator 1004 so as to modulate the signal at thesought carrier frequency (frequency f₂), for example an RF frequency inthe region of one or a plurality of GHz. The transmission system 1000also comprises elements for receiving signals: a processing circuit suchas a receiving antenna 1010, a low-noise amplifier 1012, a demodulator1014 and a baseband processing circuit 1016.

The frequency synthesis device 100 is used in conjunction with thedemodulator 1014 so as to demodulate the received RF signal intobaseband.

The invention claimed is:
 1. A frequency synthesis device, comprising: afirst generator configured to generate a periodic signal of frequencyf_(l); a second generator, coupled with the first generator andconfigured to receive as an input the periodic signal of frequency f₁and generate a signal S_(G) corresponding to a train of oscillations offrequency substantially equal to N·f₁, of a time less than T₁ =/f₁ andrepeated periodically at the frequency f₁ , where N is a whole numbergreater than 1; a third generator configured to generate, from thesignal S_(G), a periodic signal of frequency f₂ by acting as a band-passfilter applied to the signal S_(G) and rejecting from a frequencyspectrum of the periodic signal of frequency f₂ lines other than aprimary line of the periodic signal of frequency f₂, wherein saidfrequency spectrum comprises the primary line of frequencyf₂=(N+i)·f_(l), where i is a whole number.
 2. The frequency synthesisdevice according to claim 1, wherein the frequency spectrum comprisingthe primary line of frequency f₂ is a frequency spectrum of asubstantially sinusoidal signal having a substantially constantenvelope.
 3. The frequency synthesis device according to claim 1,wherein the second generator comprises at least one voltage-controlledoscillator with a free oscillation range that includes the frequencyN·f₁, the value of N being dependent on a value of first control voltageto be applied at the input of the voltage-controlled oscillator.
 4. Thefrequency synthesis device according to claim 3, wherein the secondgenerator comprises at least one switch connected to an electrical powersupply input of the at least one voltage-controlled oscillator and isconfigured to be controlled. by the periodic signal of frequency f_(l)such that the second generator generates a non-zero power supply voltageof said oscillator only for a portion of each period T_(l).
 5. Thefrequency synthesis device according to claim 3, Wherein the secondgenerator comprises at least one switch connected to an output of the atleast one votage-controlled oscillator and is configured to becontrolled by the periodic signal of frequency f₁ such that the secondgenerator breaks an electrical connection between said oscillator outputand an input of the third generator during a portion of each period T₁.6. The frequency synthesis device according to claim 1, wherein thethird generator comprises at least one injection-locked oscillatorconfigured to receive, as an input, the signal S_(G) and to be locked atleast periodically at the frequency f₂, a value of i being dependent ona value of a second control voltage configured to be applied at an inputof the injection-locked oscillator.
 7. The frequency synthesis deviceaccording to claim 1, wherein the third generator comprises at least oneband-pass filter of central frequency substantially equal to f₂.
 8. Thefrequency synthesis device according to claim 1, wherein a value of thefrequency f₁ is greater than approximately 1 GHz, or a value of thefrequency f₂, is greater than approximately 10 GHz, or oscillations ofthe signal S_(G) are sinusoidal.
 9. The frequency synthesis deviceaccording o claim 1, wherein the first generator comprises at least oneresonating device and a phase-locked. loop configured to control a phaseof the periodic signal of frequency f₁ output by a voltage-controlledoscillator of the phase-locked loop on a phase of a periodic signaloutput by the at least one resonating device.
 10. The frequencysynthesis device according to claim 1, wherein the first generatorcomprises a resonating device configured to generate the periodic signalof frequency f₁.
 11. A signal transmission and/or reception device,comprising at least one frequency synthesis device according to claim 1coupled with a modulator and/or a demodulator of the transmission and/orreception device.
 12. A frequency synthesis method, comprising:generating a periodic signal of frequency f₁; generating, from theperiodic signal of frequency f₁,a signal S_(G) corresponding to a trainof oscillations of frequency substantially equal to N·f₁, of a time lessthan T₁ =1/f₁ and repeated periodically at frequency f₁ where N is awhole number greater than 1; generating, from the signal S_(G), aperiodic signal of frequency f₂ using a band-pass filtering functionapplied to the signal S_(G) and rejecting from a frequency spectrum ofthe periodic signal of frequency f₂ lines other than a primary line ofthe periodic signal of frequency f₂, wherein said frequency spectrumcomprises the primary line of frequency f₂=(N +i)·f₁,where i is a wholenumber.
 13. A method for producing a frequency synthesis device,comprising: producing a first generator configured to generate aperiodic signal of frequency f₁; producing a second generator, coupledwith the first generator and configured to receive, as an input, theperiodic signal of frequency f₁ and to generate a signalS_(G)corresponding to a train of oscillations of frequency substantiallyequal to N·f₁, of a time less than T₁ ₌1/f₁ and repeated periodically atthe frequency f₁,where N is a whole number greater than 1; producing athird generator configured to generate, from the signal S_(G), aperiodic signal of frequency f₂ by acting as a band-pass filter appliedto the signal S_(G) and rejecting from a frequency spectrum of theperiodic signal of frequency f₂ the lines other than a primary line ofthe periodic signal of frequency f₂, wherein said frequency spectrumcomprises the primary line of frequency f_(2=(N+i)·f) ₁, where i is awhole number.